New Math path
Finally, today’s latest FPGA fabrics take a different approach in the math block, ensuring it can support 18-bit multiply-accumulate operations (Fig. 4).
Key new features as compared to earlier FPGA generations include:
- Provision of a pre-adder with a full 19-bit result. This eliminates the need for fabric adders when implementing symmetric finite-impulse-response (FIR) filters, saving power.
- Provision of an input value cascade chain. This reduces the need for fabric registers when implementing systolic FIR filters, again saving power.
- Accumulator widened to 48 bits.
In addition to the 18- × 18-bit multiplication mode, the math block should support reduced precision 9-bit operations. This includes supporting two independent 9 × 9 multiplies with no requirement for a common factor. Unlike alternative math blocks that can exchange two 18 × 18 multipliers for three 9 × 9 multipliers, this approach enables an FPGA to exchange one 18 × 18 multiplier for two 9 × 9 multipliers—a 33% improvement.
Even better, if the math block also supports a 9 × 9 dot-product mode (Fig. 4, again), the FPGA will provide an ideal solution for image-processing and convolutional-neural-network (CNN) applications. Compared to independent 9 × 9 multipliers, the dot-product operation reduces power in the following ways:
- No need for a separate fabric adder to sum the two products.
- The pre-adder is fully supported, allowing efficient implementation of symmetric 9-bit FIR filters or 2D convolution.
- All four factors are independent—designers of CNNs don’t rely on complex weight-sharing or input-sharing schemes to maximize resource and power efficiency.
New demands on FPGAs in a growing variety of mainstream, mid-range systems applications have led to fundamental changes in their design. This includes the use of new process technologies and architectures and new types of transceivers, as well as significant improvements to the basic programmable fabric logic. Fabric changes ranging from the LUT size and configuration to the design of the math block enable today’s FPGAs to meet the performance requirements of a growing range of mainstream systems while minimizing their power and cost.
About the author:
Ted Marena is the director of business development & outbound marketing at Microsemi - www.microsemi.com
This article first appeared in Electronic Design - www.electronicdesign.com